In a computer system, a compiler is utilized to convert a software program in a programming language into machine language. A processor then may execute the machine language to perform the operations designated by the software program. Although, inefficiencies arise when using compilers due to the presence of executable instructions within the machine language whose results do not affect program outputs.
One solution to overcome inefficiencies is the elimination of dead code, wherein dead code is executable program instructions whose results do not affect program output. A common scheme for removing dead code is based on program representations called static single assignment form (SSA). The SSA form can be briefly described as a form where each definition of a variable is given a unique version, and different versions of the same variable can be regarded as different program variables. Each use of a variable version can only refer to a single universal definition. When several definitions of a variable reach a common node, typically referred to as a merging node, in the control flow graph of the program, a phi function assignment statement, an=Φ(a1, a2, . . . am), is inserted to merge the variables into the definition of a new variable version an. Thus, the semantics of single reaching definitions are maintained.
The SSA based dead code elimination may be performed by adding a single bit to each instruction, wherein that bit is designated as a live bit and initially all live bits are set to false. The next step is to identify a set of critical instructions, wherein critical instructions are instructions that directly produce a program output. As long as a worklist of instructions is not empty, select an instruction from the worklist. Thereupon, walking backwards over SSA links, from use to definition, the next step is to identify all instructions that are needed as a source of the originally selected instruction. If the instruction needed for the originally selected instruction is not live, the instruction then is marked as live and added to the worklist.
The process is repeated for all instructions on the worklist. Once the worklist is empty, the value of the live bit determines if the instruction is live or dead. This provides an efficient scheme, since adding an instruction to the worklist can occur at most only one time and also designates all dead code. Although, this current approach is limited because it can only provide for the deletion of scalar instructions and fails to detect dead components. This approach is described in further detail in R. Cytron et al., Efficiently computing static single assignment form an the control depend graph, ACM Trans. On Programming Languages and Systems, 13(4), pp. 451-490, October 1991.
Another approach for the elimination of dead code is based on extending the single live bit to a set of bits based on the computation being performed with a specific number of bits as disclosed in U.S. Pat. No. 6,571,387 entitled “Method and computer program product for global minimization of sign-extension and zero-extension operations. The number of bits may not be supported by a host processor, such as a host processor might require computations to be done in sixty-four (64) bit integers, while the program instructions have been specific to thirty-two (32) bits integers. In this approach, a compiler may insert instructions to compensate for this difference. If a compiler can determine that all of the upper bits are dead code, the extra inserted instructions may be deleted.
This technique extends SSA based dead code elimination by adding a bit field to each instruction of the maximum size of a generated value. Using this bit mask, the nth bit that is used in the instruction will be set to a value of 1. During the backward walk over the SSA links, the process updates the bits in each source instruction. Therefore, once all of the SSA links have been examined, each instruction has been marked with the exact bits used. If an instruction is a sign or zero extension instruction, and the upper bits are not marked, then the instruction may be dead and thereby eliminated. This technique is limited to dead code operations that consist of sign or zero extension instructions.
In a single instruction multiple data (SIMD) processing environment, there are advantages to using a superword register, wherein a superword register includes a hardware resource that can hold a small, but more than one, number of words of data. In one exemplary orientation, the superword register can hold up to 128 bits divided into four floating point components.
Instructions that operate on superword registers operate in parallel on all components and therefore are capable of achieving very high performance provided that more than one component contains data. If a program computes an unused value in a superword component, then the value of the component is said to be dead, whereas the other components are termed live. Some compilers using superword registers fail to eliminate the dead code and therefore reduce operating efficiency due to extra un-needed components. For example, the disclosure of U.S. Pat. No. 6,571,387 does not provide for dead code elimination using a superword register. Superword registers provide improved processing times in a SIMD environment and there does not exist a dead code elimination technique with a superword register. Therefore, there exists a need for removing dead code from a superword register.